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Inter-integrated circuit (I 2 C) interface
RM0008
Bus error (BERR)
This error occurs when the I 2 C interface detects a Stop or a Start condition during a byte
transfer. In this case,
●
●
The BERR bit is set and an interrupt is generated if the ITERREN bit is set
In case of Slave: data is discarded and the lines are released by hardware:
–
–
in case of misplaced start, the slave considers it is a restart and waits for address,
or stop condition.
in case of misplaced stop, the slave reacts like for a stop condition and the lines
are released by hardware.
Acknowledge failure (AF)
This error occurs when the interface detects a non-acknowledge bit. In this case,
●
●
The AF bit is set and an interrupt is generated if the ITERREN bit is set
A transmitter which receives a NACK must reset the communication:
–
–
If Slave: lines are released by hardware
If Master: a Stop condition must be generated by software
Arbitration lost (ARLO)
This error occurs when the I 2 C interface detects an arbitration lost condition. In this case,
●
●
●
the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is
set)
the I 2 C Interface goes automatically back to slave mode (the M/SL bit is cleared). When
the I 2 C loses the arbitration, it is not able to acknowledge its slave address in the same
transfer, but it can acknowledge it after a repeated Start from the winning master.
lines are released by hardware
Overrun/underrun error (OVR)
An overrun error can occur in slave mode when clock stretching is disabled and the I 2 C
interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR
has not been read, before the next byte is received by the interface. In this case,
●
●
The last received byte is lost.
In case of Overrun error, software should clear the RxNE bit and the transmitter should
re-transmit the last received byte.
Underrun error can occur in slave mode when clock stretching is disabled and the I 2 C
interface is transmitting data. The interface has not updated the DR with the next byte
(TxE=1), before the clock comes for the next byte. In this case,
●
●
The same byte in the DR register will be sent again
The user should make sure that data received on the receiver side during an underrun
error are discarded and that the next bytes are written within the clock low time
specified in the I 2 C bus standard.
For the first byte to be transmitted, the DR must be written after ADDR is cleared and before
the first SCL rising edge. If not possible, the receiver must discard the first data.
634/995
Doc ID 13902 Rev 9
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